1. Field of the Invention
The present invention relates generally to the field of integrated circuit technology. In one aspect, the present invention relates to a circuit design and method for manufacturing a non-volatile memory device, such as an electrically erasable programmable read only memory (EEPROM) or other embedded flash memory devices.
2. Description of the Related Art
Non-volatile memory devices, such as EEPROM and flash memory, are used in computers and other electronic devices to store data and/or programming instructions that can be electrically erased and reprogrammed and that must be saved when power is removed. Embedded non-volatile memory (NVM) has become increasingly important in applications ranging from data and code storage to circuit trimming and customization. By embedding a non-volatile memory in a CMOS device, a single chip device can be manufactured and configured for a variety of applications. To combine non-volatile memory (such as flash EEPROM) into a standard CMOS process flow, additional processing steps (and associated costs) are typically added to the standard CMOS process in order to construct the additional device features (such as a floating gate or control gate) along with other system components. Some EEPROM fabrication techniques have been proposed which reduce the additional processing cost. For example, single poly EEPROM designs have been proposed which form the charge storage element (e.g., the floating gate of a MOSFET) with a single layer of polysilicon, and which form the control gate using a well that is junction-isolated from the substrate so that a bias voltage can be applied to the control gate when operating the NVM bitcell. However, single poly NVM designs typically have very large bitcells due to the requirement of electrical isolation between different wells, thereby increasing the total chip size, which translates into a cost increase for the integrated circuit. Other single poly NVM designs have been proposed to address the size concern, such as the single poly PMOS bitcell designs described in U.S. Pat. Nos. 6,617,637 and 6,711,064 in which PMOS bitcells are formed by connecting a PMOS select transistor in series with a floating gate transistor which serves as the charge storage element. To reduce the bitcell size, the PMOS bitcells described in these patents do not use a dedicated control gate to control the floating gate potential during bitcell operation, but instead add an extra ion implant step to form an erase gate that provides a mechanism to erase the memory bitcell using band to band tunneling of hot holes (as described in U.S. Pat. No. 6,617,637) or by using edge Fowler-Nordheim tunneling (as described in U.S. Pat. No. 6,711,064). Both approaches turn part of the floating gate into an N+ doped region, thereby destroying any data retention benefit of using a PMOS floating gate because the N+ portion of the floating gate in effect makes the bitcell look like an NMOS bitcell from the charge retention standpoint. In addition, the use of band-to-band tunneling of hot holes to erase the bitcell can damage the gate oxide, thereby reducing device reliability.
Accordingly, there is a need for an improved embedded NVM design and manufacturing methodology to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.